CPLD数字频率计设计报告.doc

1、摘要：本设计给出了用VHDL语言实现110KHz的频率计数器方案，显示四位十进制测量结果。包括：分频模块，时基产生与测评时序控制电路模块，待测信号脉冲计数电路，锁存与译码显示控制电路。分频模块产生用于时序控制的基础时钟，和用于控制数码管显示的时钟。时基产生与测评时序控制电路模块产生计数清零、频率计数使能、计数完成锁存等控制信号，脉冲计数模块在计数使能信号控制下进行脉冲计数，1s中所记脉冲数即为待测信号频率，译码控制模块在锁存信号控制下直接输出控制二极管显示的信号。该系统可对直接输入的110KHz信号进行测试，响应时间2S，并在测量结束后数码管上显示测试信号频率，显示时间2S，保存到下一次测量结

2、束为止。关键词：VHDL语言、分频、时基控制、待测信号脉冲计数电路、锁存与译码显示。目录摘要2一、方案设计与论证4二、系统电路设计5 （一）系统总体框图5（二）系统各模块功能的实现5 1. 分频模块功能的实现2. 时基控制模块实现3. 频率计数模块实现（1）模十计数器（2）四位十进制计数4. 锁存与译码显示模块实现三、仿真与测试分析13四、设计总结14五、附件14完整电路图14完整程序代码15参考文献22一、 方案设计与论证（一）、分频电路模块：方案一：计数分频，分别产生1Hz、50Hz、1000Hz、10KHz四种时钟信号控制时基电路的使能与清零、锁存与译码显示电路，周期测量电路，该方案要实

3、现多个分频，相对繁琐。方案二：两次分频产生10KHz信号，第一次2500分频，得到20KHz信号，再二分频得到稳定的10KHz方波。能够实现方案二中要求同时更加精确。（二）、时基产生与测评控制电路模块：方案一：依次输出清零、清零结束使能、使能结束锁存，使能大于1S时，所得到的计数值要转变后才能得到频率值，若是二进制计数，容易转变，但不易过渡到BCD码控制输出显示；若BCD码计数，不易转变。方案二：对分频模块基础时钟计时，到相应时间依次输出清零、使能、锁存信号，保证各功能依次实现互不干扰，使能1S，所得到的计数值即为频率。（三）、待测信号脉冲计数电路模块：方案一:二进制计数，得到的频率值转化成B

4、CD码，控制锁存与译码电路显示。由于频率较大，二进制位数多达13位左右，转化成BCD码相对复杂，可行度低。方案二：四个十进制计数器串联计数，实现4位十进制输出，当地位的十进制计数器进位时，高一位的计数器累加1，直接读得十进制的频率值，易于控制数码管显示。（四）、锁存与译码显示模块：方案一：将接受到的BCD码转换成控制数码管显示得信号，并在锁定信号到来时控制数码管显示，转换繁琐，但不能实现输出稳定的显示信号，不能满足设计要求。方案二：根据内部储存的数值，输出待测信号的频率值，并保存到下一次锁定信号到来接收新的频率值，根据锁定信号来接受外部传输的频率数据并锁存，保持输出控制数码管显示信号，知道下次

5、接受才改变。二、 系统电路设计（一）、系统框图（二）、系统各模块功能的实现1. 分频模块功能的实现输入50MHz ，输出cp端为10KHzss 为待测频率。为了测试该设计的功能，由于外部无已知的输入待测信号，所以也有分屏产生待测的信号。代码：dividefreENTITY dividefre IS PORT ( cp_50M: IN std_logic; cp: OUT std_logic; -10khz ss: OUT std_logic );END ENTITY;ARCHITECTURE behavior OF dividefre IS signal tout1:std_logic_vec

6、tor(11 downto 0) ; -count 2500 signal tout2:std_logic_vector(5 downto 0); -count 2 signal cp_1: std_logic; BEGIN PROCESS(cp_50M) BEGIN IF(cp_50Mevent and cp_50M=1) THEN if (tout1=100111000011) then tout1=000000000000;cp_1=1; else tout1=tout1+1;cp_1=0; end if; END IF; END PROCESS; PROCESS(cp_1) BEGIN

7、 IF(cp_1event and cp_1=1) THEN tout2=tout2+1; END IF; cp=tout2(0); ss=tout2(3); END PROCESS; END behavior;2. 时基控制模块实现：输入10KHz信号；输出clr：清零；en：使能；lock：锁定。代码：timecontrolENTITY timecontrol IS PORT ( clk: in std_logic; -10khz clr: buffer std_logic; en: buffer std_logic; lock: buffer std_logic );END ENTITY

8、;ARCHITECTURE behave OF timecontrol IS signal count:std_logic_vector(13 downto 0); begin PROCESS(clk) begin if (clkevent and clk=1) then if (count=10111001111100) then count=00000000000000; clr=1;en=0;lock=0;-11900 elsif(count=00000011001000) then count=count+1; clr=0;en=0;lock=0;-200 elsif(count=00

9、001100100000) then count=count+1; clr=1;en=0;lock=0;-800 elsif(count=00001111101000) then count=count+1; clr=1;en=1;lock=0;-1000 elsif(count=10101011111000) then count=count+1; clr=1;en=0;lock=0;-11000 elsif(count=10101111000000) then count=count+1; clr=1;en=0;lock=1;-11200 elsif(count=1011100001100

10、0) then count=count+1; clr=1;en=0;lock=0;-11800 else count=count+1;clr=clr;en=en;lock=lock; end if; end if; end process;END behave;3. 频率计数模块实现：（1）模十计数器：ci：使能；nrest：清零；clk：计数脉冲。co：进位。qcnt:BCD码对应计数值。代码：cntm10ENTITY cntm10 is port ( ci : in std_logic; nreset : in std_logic; clk : in std_logic; co : out

11、 std_logic; qcnt : buffer std_logic_vector(3 downto 0) );end cntm10;architecture behave of cntm10 is beginprocess (clk,nreset) begin if (nreset=0) then qcnt=0000;elsif (clkevent and clk=1) then if (ci=1) then if (qcnt=9) then qcnt=0000; co=1; else qcnt=qcnt+1; co=0; end if; end if;end if;end process

12、;end behave;（2）四位十进制计数：四个十进制计数器串联，clr、en是共同控制端，clk从最低位输入开始计数。得到输出的四位十进制数（BCD码）。代码：frequtestENTITY frequtest IS PORT ( ss :in std_logic; -in clk:in std_logic; -10khz clr:in std_logic; -set0 en :in std_logic; -2minite q3,q2,q1,q0:out std_logic_vector(3 downto 0) );END ENTITY;architecture behave of fre

13、qutest is component cntm10 port ( ci : in std_logic; nreset : in std_logic; clk : in std_logic; co : out std_logic; qcnt : buffer std_logic_vector(3 downto 0) );end component;signal co1,co2,co3,co4 :std_logic; BEGIN u0:cntm10 port map (en,clr,ss,co1,q0); u1:cntm10 port map (en,clr,co1,co2,q1); u2:cn

14、tm10 port map (en,clr,co2,co3,q2); u3:cntm10 port map (en,clr,co3,co4,q3);end behave;4. 锁存与译码显示模块实现：cp为扫频的10KHz脉冲，lock是锁存信号，q对应四位要显示得值。 Seg为显示得段码，scan为控制的显示位使屏幕动态改变。代码：displayENTITY display IS PORT ( cp: IN std_logic; - 10khz lock: IN std_logic; q3,q2,q1,q0:in std_logic_vector(3 downto 0); seg: OUT

15、std_logic_vector(6 downto 0); scan: OUT std_logic_vector(3 downto 0) );END display;ARCHITECTURE behavior OF display IS SIGNAL state:integer range 0 to 3; SIGNAL sel:std_logic_vector(3 downto 0); signal p0,p1,p2,p3:std_logic_vector(3 downto 0); BEGIN process(lock) begin if(lockevent and lock=1) then

16、p0=q0; p1=q1; p2=q2; p3=q3; end if; end process; PROCESS(cp) BEGIN IF(cpevent and cp=1) THEN if state=3 then state=0; else state sel sel sel sel seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg seg

17、 seg seg seg seg seg=0000000; end case; END IF; END PROCESS; scan=sel;END behavior;三、仿真与测试分析分频：由于对50MHz进行5000分频，时间过长，但用相同的程序修改参数将其缩短可以看到理想的输出仿真电路：输出方波信号。时基产生与测频控制电路：先给出clr的清零信号，然后en在1S钟内使能高电平，接着lock发送锁定信号。如此循环。由于仿真时间也过长，所以同样改小其值，可以看到理想的输出波形。待测信号脉冲计数电路：通过四个模十计数器实现。模十计数器如图；将四个模十计数器连接得到四位数的频率计数器，先在clr信

18、号下统一清零，在en效的1s内，对输入ss计数：四、 设计总结通过各模块的相互连接工作可以很好得实现110KHz频率的测试，直接输入要测试的频率便可得到测试结果，在数码管上显示。可以很好得实现响应时间在2S以内，显示时间大于1S，具有记忆显示功能，在测量过程中不断刷新，等到测量结果结束才显示测量结果，并保存到下一次测量结束。五、 附件（一） 完整电路图（二）VHDL设计文件 完整程序代码：*顶层文件*library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_signed.all;ENTITY frequent IS port ( C

19、P_50M:IN std_logic; seg : out std_logic_vector(6 downto 0); scan: out std_logic_vector(3 downto 0) );END entity;ARCHITECTURE content OF frequent iscomponent dividefre is PORT ( cp_50M: IN std_logic; cp: OUT std_logic; -10khz ss: OUT std_logic );end component;component timecontrol is PORT ( clk: in s

20、td_logic; -10khz clr: buffer std_logic; en: buffer std_logic; lock: buffer std_logic );end component;component frequtest is PORT ( ss :in std_logic; -in clk:in std_logic; -10khz clr:in std_logic; -set0 en :in std_logic; -2minite q3,q2,q1,q0:out std_logic_vector(3 downto 0) );end component;component

21、display is PORT ( cp: IN std_logic; - 10khz lock: IN std_logic; q3,q2,q1,q0:in std_logic_vector(3 downto 0); seg: OUT std_logic_vector(6 downto 0); scan: OUT std_logic_vector(3 downto 0) );end component; signal cp,cp1,rst,enable,lok,ss:std_logic; signal qa0,qa1,qa2,qa3:std_logic_vector(3 downto 0);

22、begin a0: dividefre port map(CP_50M,cp,ss); a1: timecontrol port map(cp,rst,enable,lok); a2: frequtest port map(ss,cp,rst,enable,qa3,qa2,qa1,qa0); a3: display port map(cp,lok,qa3,qa2,qa1,qa0,seg,scan); end content;*10KHz分频模块*library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;EN

23、TITY dividefre IS PORT ( cp_50M: IN std_logic; cp: OUT std_logic; -10khz ss: OUT std_logic );END ENTITY;ARCHITECTURE behavior OF dividefre IS signal tout1:std_logic_vector(11 downto 0) ; -count 2500 signal tout2:std_logic_vector(5 downto 0); -count 2 signal cp_1: std_logic; BEGIN PROCESS(cp_50M) BEG

24、IN IF(cp_50Mevent and cp_50M=1) THEN if (tout1=100111000011) then tout1=000000000000;cp_1=1; else tout1=tout1+1;cp_1=0; end if; END IF; END PROCESS; PROCESS(cp_1) BEGIN IF(cp_1event and cp_1=1) THEN tout2=tout2+1; END IF; cp=tout2(0); ss=tout2(3); END PROCESS; END behavior;*时基控制模块*library ieee;use i

25、eee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY timecontrol IS PORT ( clk: in std_logic; -10khz clr: buffer std_logic; en: buffer std_logic; lock: buffer std_logic );END ENTITY;ARCHITECTURE behave OF timecontrol IS signal count:std_logic_vector(6 downto 0); begin PROCESS(clk) begin if

26、(clkevent and clk=1) then if (count=1111101) then count=0000000; clr=1;en=0;lock=0;-125 elsif(count=0001010) then count=count+1; clr=0;en=0;lock=0;-10 elsif(count=0010100) then count=count+1; clr=1;en=0;lock=0;-20 elsif(count=0011110) then count=count+1; clr=1;en=1;lock=0;-30 elsif(count=1100100) th

27、en count=count+1; clr=1;en=0;lock=0;-100 elsif(count=1101110) then count=count+1; clr=1;en=0;lock=1;-110 elsif(count=1111000) then count=count+1; clr=1;en=0;lock=0;-120 else count=count+1;clr=clr;en=en;lock=lock; end if; end if; end process;END behave;*频率测试模块*library ieee;use ieee.std_logic_1164.all

28、;use ieee.std_logic_unsigned.all;ENTITY frequtest IS PORT ( ss :in std_logic; -in clk:in std_logic; -10khz clr:in std_logic; -set0 en :in std_logic; -2minite q3,q2,q1,q0:out std_logic_vector(3 downto 0) );END ENTITY;architecture behave of frequtest is component cntm10 port ( ci : in std_logic; nrese

29、t : in std_logic; clk : in std_logic; co : out std_logic; qcnt : buffer std_logic_vector(3 downto 0) );end component;signal co1,co2,co3,co4 :std_logic; BEGIN u0:cntm10 port map (en,clr,ss,co1,q0); u1:cntm10 port map (en,clr,co1,co2,q1); u2:cntm10 port map (en,clr,co2,co3,q2); u3:cntm10 port map (en,clr,co3,co4,q3);end behave;*译码显示模块*library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_unsigned.all;ENTITY display IS PORT ( cp: