个人作品翻译外文文献电子设计自动化.doc

《个人作品翻译外文文献电子设计自动化.doc》由会员分享，可在线阅读，更多相关《个人作品翻译外文文献电子设计自动化.doc（21页珍藏版）》请在沃文网上搜索。

1、附录B 翻译原文Electronic design automationKeyword EDA; IC;VHDL language; FPGAPROCESS DESCRIPTION Three obstacles in particular bedevil ic designers in this dawn of the system on a chip. The first is actually a shortfall-the hardware and software components of the design lack a unifying language. Then, as

2、the number of logic gates per chip passes the million marks, verification of a designs correctness is fast becoming more arduous than doing the design itself. And finally, not only gate counts but chip frequencies also are climbing, so that getting a design to meet its timing requirements without to

3、o many design iterations is a receding goal. As is the wont of the electronic design automation (EDA) community, these concerns are being attacked by start-up companies led by a few individuals with big ideas and a little seed money.PARLEZ-VOUS SUPERLOG?A system on a chip comprises both circuitry an

4、d the software that runs on it. Such a device may contain an embedded processor core running a software modem. Most often, after the chips functionality is spelled out, usually on paper, the hardware com- potent is handed off to the circuit designers and the software is given to the pro- grammars, t

5、o meet up again at some later date. The part of the chips functionality that will end up as logic gates and transistors is writ- ten in a hardware design language-Virology or VHDL, while the part that will end up as software is most often described in the programming language C or C+. The use of the

6、se disparate languages hampers the ability to describe, model, and debug the circuitry of the IC and the software in a coherent fashion.It is time, many in the industry believe, for a new design language that can cope with both hardware and software from the initial design specification right throug

7、h to final verification. Just such a new language has been developed by Co-Design Automation Inc., San Jose, Calif. Before launching such an ambitious enterprise, cofounders Simon Davidmann, who is also chief operating officer, and Peter Flake ruled out the usefulness of extending an existing langua

8、ge to meet system-on-chip needs. Among the candidates for extension were C, C+, Java, and Verilog. A design language should satisfy three requirements, maintained Davidmann. It should unify the design process. It should make designing more efficient. And it should evolve out of an existing methodolo

9、gy. None of the existing approaches filled the bill. So Davidmann and Flake set about developing new co-design language called Superlog. A natural starting point was a blend of Virology and C since from an algorithm point of view, a lot of Virology is built on C, explained Davidmann. Then they spice

10、d the blend with bits and pieces of VHDL and Java. From Virology and VHDL, Superlog has acquired the ability to describe hardware aspects of the design, such as sequential, combinatorial, and multivalued logic. From C and Java it inherits dynamic processes and other software constructs. Even functio

11、ns like interfaces, protocols, and state machines, which till now have often been done on paper, can be described in the new language. To support legacy code written in a hardware description or programming language, Superlog allows both Virology and C modules to be imported and used directly.It is

12、important for the language to be in the public domain, according to Davidmann. The company has already begun to work with various standards organizations to this end. Not to be overlooked is the need for a suite of design tools based on the language. Recently Co-Design identified a number of electro

13、nic design automation companies, among them Magma Design Automation, Sente, and Viewlogic, that will develop tools based on Superlog. Co-Design will also develop products for the front end of the design process.ARACE TO THE FINISH Not everyone is convinced that a new language is needed. SystemC, a m

14、odeling platform that extends the capabilities and advantages of C/C+ into the hardware domain has been proposed as an alternative. Such large and powerful companies as Synopsys, Coware, Lucent Technologies, and Texas Instruments have banded together under the Open SystemC Initiative to promote thei

15、r version of the next-generation design platform. To get SystemC off to a running start, the group offers a modeling platform for download off their Web site free of charge. Their hope is also to make their platform the de facto standard. The rationale for developing SystemC was straightforward, acc

16、ording to Joachim Kunkel, general manager and vice president of the System Level Design Business Unit at Synopsys. It was to have a standard language in which semiconductor vendors, IP vendors, and system houses could exchange system-level IP and executable specifications, and the electronic design

17、automation industry could develop interoperable tools. Supporters of SystemC believe that the would-be standard has to be based on C+ because it allows capabilities to be added to it without leaving the language standard, Kunkel told JEEE Spectrum. Most software developers use C+ and many systems de

18、velopers use C+ already to describe their systems at a behavioral level. But till now it has not been possible to describe hardware using the language.The developers of SystemC have solved that problem by defining new C+ class libraries and a simulation kcrne1 that bring to C+ all of the capabilitie

19、s needed to describe hardware. These new classes implement new functionality, explained Kunkel. For example, bit vectors-strings of zeros and ones-and all the operations that you would do on them. The SystemC developers also provided a class of signed and unsigned numbers, the notion of a signal, an

20、d other concepts needed to model hardware. There are still some holes, however. For example, it is still not possible to synthesize a gate-level netlist from a SystcmC description. Rut synthesis tools for SysteniC would he a natural result of broad acceptance of the language within the user communit

21、y, according to Kunkel. It remains to be seen whether SystemC or Superlog wins out in the end. Least desirable would be an outcome like the impasse between Virology and VHDL, in which both prevailed, forcing electronic design automation vendors to support both platforms in a wasteful duplication of

22、effort. THE VERIFICATION NIGHTMARE If todays complex ICs are tough to design, they are very much tougher to verify. A variety of tools are available, each with its pros and cons. Emulation translates a design into field-programmable gate arrays (FPGAs). Presumably, if the array works as planned, the

23、 final chip will also. The emulation platform also enables designers to try 0111 the software that will run on the ASIC. The approach, though, is slow. Typical emulation systems run at a few megahertz. At roughly one million cycles per second, designers arc not getting cnough performance out of thei

24、r emulation systems to verify or understand some of the things that are going on with video generation or high bandwidth communications, said John Gallagher, director of marketing for Synplicity Inc., Sunnyvale, Calif. They must process a large number of operations to ensure their functionality is c

25、orrect, he added. The reason that emulation systems are so slow, according to Gallagher, is that they route the design through many FPGAs and many boards. Simplicity solution is to use a few high-end FPGAs having over one million gates running at 100 MHz. Typically, a million FPGA gates translates i

26、nto 200 000 ASIC gates. Putting nine such chips on a board in a three-by-three array allows designers to represent up to 1.8million ASlC gates. And routing delays are greatly curtailed because each chip is no more than two hops away from any other chip in the array. The company% product, called Cert

27、ify, is not intended to compete with reconfigurable emulation systems, which are very effective at debugging designs during the internal design process, explained Gallagher. Rather, it is a true prototype of the system, running at speeds that may approach the real thing. Certify handles three fundam

28、ental operations, said Gallagher. The first is partitioning, or breakings up the ASIC register transfer level (RTL) code into different FPGAs. It does synthesis, turning the RTL code into ASIC gates equivalent to the final ASIC gates. Then it does timing analysis. We havent just linked together the

29、different tools,” he explained. We have taka our synthesis algorithms, between the partitioning capabilities, and laid the timing analysis across that. In addition to emulation, two complementary approaches to design verification are simulation and model checking, a type of formal verification. Simu

30、lation applies vectors to a software model of a design and checks to sec if the output has the correct value. The approach is straightforward, but is becoming increasingly tortuous as designs become more complicated and the number of possible test vectors mushrooms. So recently, electronic design au

31、tomation companies have been turning to model checking to prove that designs are correctly done. The sticking point with model checking is its great difficulty of use. It is not for most engineers, said Simon Napper, chief operating officer OF Innol-ogic Systems Inc., San Jose, Calif. The usage mode

32、l is very difficult-it checks properties. But the designer isnt familiar with what P property is-he is used to simulation and static timing. As a remedy, InnoLogic developed a symbolic simulation tool, which blends simulation and formal verification. It is a Virology simulator except instead of send

33、ing Is and Os through the logic, the too1 propagates symbol or symbols plus binary values.The user gains improved functional coverage dong with much faster verification. To illustrate, to completely verify a fourbit adder would require 256 binary vectors-and take 256 simulation cycles. With symbols,

34、 it takes just one cycle.Just as with formal verification, there are limits to the complexity of the circuits that symbolic simulation can completely verily. Both have trouble with multipliers, for example. A model checker will grind and grind and never produce a result, explained Napper. But in our

35、 tool we take some symbol inputs and switch them to binary values, that reduces the job from a 32- to a 16-bit multiplier. And we report to the user that we were able to verify the upper the operands. InnoLogic has announced two Versifies of symbolic simulation. ESI-XV verifies designs written in Vi

36、rology. EXP-CV is meant for custom designs and memory blocks. THE TIME IS RIGHT Though the design of ICs with semiconductor geometries below 0.25 pm face challenges throughout development, some of the biggest hurdles occur during physical design, when the gates are placed on the chip and the interco

37、nnects are routed between them Problems occur here for a number of reasons. First, the capacitance, resistance, and inductance of the interconnects cannot be ignored, as they were in older, larger technologies. Crosstalk between interconnects; now closer together, must also be controlled. Several it

38、erations through synthesis and placement may be necessary to achieve the required timing, if it can be accomplished at all. The solution proposed by Monterey Design Systems Inc., Sunnyvale, Calif., is called global design technology. This proprietary computing approach simultaneously explores, analy

39、zes, and optimizes all aspects of the physical design. The tint product containing the technology is Dolphin, which was announced in April of last year. Dolphin simultaneously places and router each gate and flip-flop using the results or the analysis and maintaining all specified constraints. (Most

40、 place- and-route tools sequentially analyze the layout for each type of constraint.) It performs timing and logic optimization for every placement move.Timing closure is top priority for developers of the Blast Fusion physical design system from Magma Design Automations., Cupertino, Calif. Its meth

41、odology, called FixedTiming, brings timing within specified limits without iterating between synthesis and physical design .Basically, he approach fixes timing first, then adjusts cell sizes to achieve the timing requirements. Varying the cell sizes always he tool to supply the right drive strength

42、or the load.EDA ON THE WEB As established electronic design automation companies try to sort out how to utilize the internet in their product Inks, smaller, more agile companies and start-ups arc coining up with innovative products and services, mainly in the areas or design management. A pioneer in

43、 this area is Synchronicity Inc., a virtual company headquartered in Marlboro, Mass. Synchronicity is now being joined by other companies seeking to use the internet to advantage. The concern of CCAES.COM, Milpitas, Calif a provider of Web-based engineering tools for; design automation, is the extra

44、ction of useful information about ICs, chip sets, and boards from suppliers Web sites. The issue, according to Michael Bitzko, president of the company, is that designers of products based on there components need to be able to obtain information about them quickly and route it to their engineering,

45、 manufacturing, and procurement departments as quickly as possible. In a nutshell,” said Bitzko, people used to take weeks to get data sheets. Then along cane the Web and PDF-formatted documents. But in order to create, ray, schematic symbols and footprints fur printed circuit boards, information fr

46、om PDF documents must often be reentered-a costly and time-consuming process when time to infarct is a concern. CCAES.COMs products are based on the electronic component interchange (ECIX) standard developed by EDA standards organization SI, Austin, Texas, and on the Extensible Markup Language (XML)

47、, that allows the creation or Web-bask documents having (more functionality than with the conventional Hypertext Markup Language (HTM1.). The companys products include QuickData Server, a parametric search engine for electronic component information, and Quickdata Miner, which transform information

48、contained in PDF data sheets into a usable form. The mission or Genedax Inc., Portland, Ore. is to use the Web to increase designed ability to create and manage large, complex designs, to iron design ICLISC, and to improve access to intellectual property. The company plans to announce a product in t

49、he first quarter or the year. John Ott, vice president of sales and marketing, told Sprctmni that its products will be based on the operating systems and browsers developed by Microsott Corp., Redmond, Wash. Also, the company supports a collaborative Web site, that shows what the technology can do. The site includes a search engine based on AltaVista technology that searches the Web sites of companies related to design auto illation. Ott elabora